In recent years, development has been progressed for memories including a ferroelectric capacitor which stores information using the hysteresis characteristic of a ferroelectric material (Ferroelectric Random Access Memory: hereinafter referred to as “FeRAM”). A FeRAM is a nonvolatile memory in which information is not erased even after power is turned off, and has excellent characteristics of achieving high integration, high speed driving, high durability, and low power consumption.
As a ferroelectric film material of a ferroelectric capacitor, mainly used is a ferroelectric oxide having the perovskite crystal structure such as PZT (Pb(Zr,Ti)O3) or SBT (SrBi2Ta2O9) whose residual polarization amount is large. The residual polarization amounts of these ferroelectric oxides are approximately 10 to 30 μC/cm2.
FIG. 1 is a schematic view depicting an example of a semiconductor device having a conventional ferroelectric capacitor. A semiconductor substrate 10 is separated into multiple element regions by an element isolation film 11. A transistor T and other elements, which constitute an electronic circuit, are formed in each element region.
The transistor T includes a pair of high concentration impurity regions (source/drain) 18 each of which is formed by selectively injecting an impurity into the semiconductor substrate 10, a gate insulating film (unillustrated) formed on a region between the pair of these high concentration impurity regions 18, and a gate electrode 14 formed on the gate insulating film. A stopper layer 20 is formed on the semiconductor substrate 10. This stopper layer 20 covers the transistor T and the element isolation film 11. In addition, a first interlayer insulating film 21 is formed on the stopper layer 20. A W (tungsten) plug 22 is formed in this interlayer insulating film 21, and the W plug 22 reaches one of the high concentration impurity regions 18 of the transistor T from the upper surface of the interlayer insulating film 21.
A ferroelectric capacitor 30 is formed on the interlayer insulating film 21, and has a structure in which a lower electrode 26a, a ferroelectric film 27, and an upper electrode 28a are stacked in this order from the bottom. This ferroelectric capacitor 30 is covered with a second interlayer insulating film 31 formed on the first interlayer insulating film 21.
Wirings 37 of a first wiring layer are formed on the second interlayer insulating film 31. One of these wirings 37 is electrically connected to the upper electrode 28a through a W plug 33a extending from the upper surface of the interlayer insulating film 31 and being connected to the upper electrode 28a of the ferroelectric capacitor 30. Another wiring 37 is electrically connected to the lower electrode 26a through a W plug 33b extending from the upper surface of the interlayer insulating film 31 and being connected to the lower electrode 26a of the ferroelectric capacitor 30. Still another wiring 37 is electrically connected to the W plug 22 through the W plug 33c penetrating the interlayer insulating film 31 in a vertical direction.
A third interlayer insulating film 40 is formed on the wirings 37 of the first wiring layer and the second interlayer insulating film 31. Wirings 42 of a second wiring layer are formed on this third interlayer insulating film 40. Some predetermined ones of these wirings 42 are each electrically connected to the wirings 37 of the first wiring layer through a W plug 41 penetrating the interlayer insulating film 40 in the vertical direction.
A fourth interlayer insulating film 46 is formed on the wirings 42 of the second wiring layer and the third interlayer insulating film 40. Wirings 48 of a third wiring layer and a terminal 49 are formed on this fourth interlayer insulating film 46. A predetermined one of the wirings 48 of the third wiring layer is electrically connected to the wiring 42 of the second wiring layer through a W plug 47 penetrating the interlayer insulating film 46 in the vertical direction.
On the wirings 48 of the third wiring layer and the fourth interlayer insulating film 46, a first passivation film 51, a second passivation film 52, and a protection film are formed in this order from the bottom. Then, the first passivation film 51, the second passivation film 52, and the protection film 53, which are formed on the terminal 49, are selectively removed to expose the surface of the terminal 49.
As depicted in this FIG. 1, conventionally, the high concentration impurity region 18 of the transistor T and the wiring 37 of the first wiring layer are connected to each other through the two W plugs 22 and 33c, which are lined up in the vertical direction. This configuration is employed because: the two interlayer insulating films 21 and 31 are present between the wiring 37 of the first wiring layer and the high concentration impurity region 18; the wiring 37 of the first wiring layer and the high concentration impurity region 18 has such a long distance therebetween; so that long-time etching needs to be performed to form a contact hole extending from the upper surface of the interlayer insulating film 31 and reaching the high concentration impurity region 18; and such long-time etching may badly damage the ferroelectric capacitor 30. In short, with the long etching time, characteristic of the ferroelectric capacitor 30 deteriorates by receiving plasma damages. In addition, if contact holes respectively reaching the upper electrode 28a and the lower electrode 26a and a contact hole reaching the high concentration impurity region 18 are formed simultaneously, the upper electrode 28a and the lower electrode 26a are etched before the contact hole reaching the high concentration impurity region 18 is completed. Instead, the contact hole reaching the high concentration impurity region 18 may be formed alone. In this case, however, a problem arises that an etching amount is not stabilized (controlled etching is difficult) because of a high aspect ratio (an etching depth is too large relative to the diameter of the contact hole).
As depicted in FIG. 1, the two W plugs 22 and 33c, which are formed individually, connect the wiring 37 of the first wiring layer and the high concentration impurity region 18, whereby a damage given to the ferroelectric capacitor 30 during the etching of the interlayer insulating films can be suppressed. Thus, preferable ferroelectric characteristic can be obtained.
In this case, as depicted in FIG. 1, the size (diameter) of the W plug 22 on a lower side is designed to be slightly larger than the size (diameter) of the W plug 33c on an upper side. This design is made to securely form a contact hole right above the W plug 22 even if slight misalignment occurs when a contact hole reaching the W plug is formed from the upper surface of the interlayer insulating film 31 by the photolithography method. In this way, the interlayer insulating film 21 can be prevented from being etched when the contact hole is formed in the interlayer insulating film 31.
Note that patent documents 1 to 4 disclose prior arts which are considered relevant to the embodiments discussed herein. Patent document 1 discloses a semiconductor device in which: a silicide pad having a shape larger than that of a plug formed of polysilicon (polysilicon plug) is formed on top of the polysilicon plug; and a plug in an upper layer and the polysilicon plug are electrically connected each other through the silicide pad.
Patent document 2 discloses a semiconductor device manufacturing method involving: sequentially forming a first conductive film and a second conductive film on the entire upper surface of a substrate after forming a plug; patterning the second conductive film in a predetermined shape; performing isotropic etching of the first conductive film by using the second conductive film as a mask, thereby to form a connection pad, made of the first conductive film, on a predetermined plug. The plug and the second conductive film (wiring) are electrically connected each other through the connection pad.
Patent document 3 discloses a structure in a semiconductor device having a stack-type capacitor. In this structure, a contact hole between an impurity region on a substrate surface and an aluminum wiring is filled with polysilicon. Patent document 4 discloses a method for forming a contact plug having a large upper diameter, by performing isotropic etching and anisotropic etching in combination.
As described above, in consideration of misalignment occurring in the photolithography process, the size (diameter) of the plug 22 has been conventionally designed to be slightly larger than the size (diameter) of the contact hole formed thereon. However, with further size reduction (high integration) of a semiconductor device, the position of the contact hole 31a has been sometimes misaligned with the position of the plug 22 as depicted in FIG. 2A.
When the position of the contact hole 31a is misaligned with the position of the plug 22 as described above, a portion, near the upper portion of the plug 22, of the interlayer insulating film 21 is etched when the contact hole 31a is formed, and thus a depression 21a is generated. Usually, when the formation of the contact hole 31a is completed, a barrier metal (glue layer) is formed on the entire surface to cover the wall surface of the contact hole 31a. However, as depicted in FIG. 2B, in the portion where the depression 21a is formed, the barrier metal 33g is not filled into the bottom of the depression 21a. Accordingly, the depression 21a is left unfilled.
When moisture or impurities accumulate(s) in this depression 21a, the moisture or impurities diffuse(s) into the interlayer insulating films 21 and 31 during a heat treatment process performed thereafter, and reaches the ferroelectric film 27. This causes serious deterioration of the characteristic of the ferroelectric capacitor 30. In addition, even if a semiconductor device has no problems right after being manufactured, long term use of the semiconductor device may cause the moisture or impurities to diffuse into the interlayer insulating films 21 and 31, and thereby lead to deterioration of the characteristics of the ferroelectric capacitor 30 or the transistor T.
The size of the plug 22 may be further increased in order to prevent the depression 21a from being generated. However, if so, a problem arises that the size reduction of a semiconductor device is disturbed.    Patent document 1: Japanese Laid-open Patent Publication No. 2001-210711    Patent document 2: Japanese Laid-open Patent Publication No. 10-289950    Patent document 3: Japanese Laid-open Patent Publication No. 05-243517    Patent document 4: Japanese Laid-open Patent Publication No. 08-236476